Variables are objects used to store intermediate values between sequential VHDL statements.
Variables are allowed only in processes, functions and procedures and are always local to them.
Variables are much like variables in conventional software programming language.
They immediately take on and store the value assigned to them.
Variables are commonly not understood and are therefore not used much.Variables can be
very powerful when used correctly. Here we explain on how to properly use variables. Variables are used to carry combinatorial signals (when used properly, otherwise they can infer sequential logic also) within a process.Variables are updated differently than signals in simulation and synthesis.
In simulation, variables are updated immediately, as soon as an assignment is made.This differs from how signals are updated in simulation. Signals are not updated until all processes that are scheduled to run in the current delta cycle have executed. A variable can be used to carry a combinatorial signal within both a clocked process and a combinatorial process.
This is how synthesis tools treat variables – as intended combinatorial signals but the way coding is done can change the synthesis results. Especially, the order in which signal and variable assignments are made results in the difference.
Figure below shows how to use a variable correctly. In this case, the variable v maintains its combinatorial intent of a simple two-input and-gate that drives an input to an or-gate for both the a and b registers.
Variables are allowed only in processes, functions and procedures and are always local to them.
Variables are much like variables in conventional software programming language.
They immediately take on and store the value assigned to them.
Variables are commonly not understood and are therefore not used much.Variables can be
very powerful when used correctly. Here we explain on how to properly use variables. Variables are used to carry combinatorial signals (when used properly, otherwise they can infer sequential logic also) within a process.Variables are updated differently than signals in simulation and synthesis.
In simulation, variables are updated immediately, as soon as an assignment is made.This differs from how signals are updated in simulation. Signals are not updated until all processes that are scheduled to run in the current delta cycle have executed. A variable can be used to carry a combinatorial signal within both a clocked process and a combinatorial process.
This is how synthesis tools treat variables – as intended combinatorial signals but the way coding is done can change the synthesis results. Especially, the order in which signal and variable assignments are made results in the difference.
Figure below shows how to use a variable correctly. In this case, the variable v maintains its combinatorial intent of a simple two-input and-gate that drives an input to an or-gate for both the a and b registers.
Figure:: Correct Use of Variables
In Figure below, you read from the
variable incorrect_v before you
assign to it. Thus, incorrect_v uses its previous value, therefore inferring a
register because that's the only way to have previous value available inside Sequential process. Had this been a combinatorial
process, a latch would have been inferred.
Conclusion/Rule for variable usage ::
Always make an assignment to a variable before
it is read. Otherwise, variables will infer either latches (in combinatorial
processes) or registers (in clocked processes) to maintain their previous
value. The primary intent of a variable
is for a combinatorial signal.
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