System On Chip Architecture

SOC covers many topics

– processor: pipelined, superscalar, VLIW, array, vector
– storage: cache, embedded and external memory
– interconnect: buses, network-on-chip
– impact: time, area, power, reliability, configurability
– customisability: specialized processors, reconfiguration
– productivity/tools: model, explore, re-use, synthesise, verify
– examples: crypto, graphics, media, network, comm, security
– future: autonomous SOC, self-optimising/verifying design

THE NEED OF FORMAL VERIFICATION

In VLSI design flow, the Verification tasks on Chip-RTL and Synthesis on the Chip-RTL
are done Parrallely by different teams. There is a Point in the Design cycle when the RTL gets freezed - which means the Chip-RTL will not be re-synthesized after that.

But the Verification activities are going on as usual which may lead to identification of bugs or connectivity issues between different blocks of the Chip.

Now, these bugs or identified connectivity issues are also to be implemented in RTL-code as well as synthesized RTL (Netlist).

There are tools for doing so. These tools add gates, wires, flip flops etc in the Synthesized Netlist as per the Bug or connectivity issue.

Formal Verification is the Process of Verifying that there is no mismatch between the Synthesized Netlist and Updated/corrected RTL Code and both are equivalent.

As Updated/Corrected RTL is approved by the Design Verification Team , Formal verification is a sure-shot method of verifying that the smae changes are implemented in the Synthesized RTL (Netlist) which is the one to be finally given to Physical Design Team for Final Product/Chip implementation.