Thursday, November 6, 2014

VERILOG :: Widely used Hardware Description Language - Important Concepts (Initial draft)


1. Each bit in a register can take on one of four values: 0, 1, x, or z. These are the only values a        register can contain.

2.  Is this declaration of registers correct ?
      reg [5:0] x, [5:0] y;
      No !!
      reg [5:0] x, y;
     This is Correct !!

3.  and (a,b,c), (d,e,f);  
     This is also correct instantiation of AND gate !!

4. The primary rule with continuous assignments is that the left-hand side must be a net. The reason for this rule is that registers get values at discrete times, but nets are always driven by a value. Changes to a net may happen asynchronously, any time anything on the right-hand side changes, the left-hand side may change its value

5. Continuous assignments are very similar to port connections between parent and child modules

6. Time can elapse during the execution of a task, according to time and event controls in the task definition

7. Function arguments are also restricted to inputs only. Output and inout arguments are not allowed