Metastability .......

There are 2 parameters associated with every flip-flop - setup and hold time.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable (in between 0 and 1) : this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. The below diagram explains it better ::

But the question is why does flip-flop goes into metastable state whenever set-up or hold time is violated ?

To answer this, we should understand the internal working of flipflop at the transistor level.

Consider the flip-flop in Figure below. Assume that the clock is low, node A is at 1, and input D changes from 0 to 1. As a result, node A is falling and node B is rising. When the clock rises, it disconnects the input from node A and closes the A B loop. If A and B happen to be around their metastable levels, it would take them a long time to diverge toward legal digital values.In fact, one popular definition says that if the output of a flip-flop changes later than the nominal clock-to-Q propagation delay, then the flip-flop must have been metastable

some solutions to the problem of metastability ::

1. Using faster flipflops decreases the setup and hold times of the flipflop, which in turn

decreases the time window that the flipflop is vulnerable to metastability

2. Using 2 flop/ 3 flop Synchronizers