Introduction
Static timing analysis is an important step in VLSI design flow for analyzing the performance
of a digital design. Static Timing Analysis is a technique for estimating the delay, maximum
operating frequency of a digital circuit and finding any timing violations in the digital circuit
without simulation by ensuring that every register to register path in the design does not
violate the setup and hold time of every flip flop. An accurate and efficient static timing
analysis has many benefits, such as providing quick and efficient information to enhance the
design performance and easing the design debugging procedure. The basic concepts required
for understanding the complete Static Timing Analysis are discussed first. These concepts are
Set Up and Hold Time Violations, False Paths, Multicycle paths and Clock skew.These concepts
are then used to understand the calculations of path delay, maximum operating frequency and
the requirements for the correct working of the digital circuit.
Set Up and Hold Time Violations
It is a fundamental design principle that timing must satisfy every flip-flop's setup and hold time
requirements, otherwise the flip-flop may go into metastable state ,where the output of flip flop
is unpredicatble. Set up time is the time period for which the data at the data input of the flip
flop must remain stable before the triggering of the flip-flop by clock edge.
Setup violations occurs when the data path is too slow compared to the clock speed.
The best way to fix the setup violations is by reducing the delay in the data path
Hold time is the time period for which the data at the data input
of the flip flop must remain stable after the triggering of the flip-flop by clock edge.
Hold violations occurs when data is too fast when compared to the clock speed.
Hold violations can be fixed by adding more delay to the data path.
False paths
A false path is a path, which exists in the chip but it would never be exercised in the operation of the chip. STA tools can report violations on false paths because there is no knowledge of circuit function. so STA tools needs to be informed about false paths in the circuit so that it should not report any violation. As the STA tool determines delay, it considers only the paths that actually affect the output. If the path is never activated or sensitized, it can't contribute to the delay. Any path that doesn't change or doesn't affect the operation of the circuit should be labeled as false path
Multi-Cycle Paths
A Multi-cycle path in a design is a Register-to-Register path, through some combinational logic where if the source register changes, the path will require N number of clock cycles (where N>1) before the computation is propagated to the destination register
Clock Skew
clock skew is a phenomenon in synchronous circuit in which the clock signal arrives
at different flip flops at different times. This can be caused by many different things,
such as wire-interconnect length, clock gating, temperature variations and differences in input
capacitance on the clock inputs of devices using the clock. The clock skew can be
positive or negative depending on how the clock-tree is made for the circuit.
clock skew plays an important role in determining the maximum operating frequency of the circuit.
Timing Constraints
Timing constraints are how the designer tells the STA tool about the timing behavior
of the ASIC. The three minimum constraints are defining the clock, input delay, and
output delay. There are four types of timing paths available. They are :
- Input to Register (Sync),
- Register to Register (Sync),
- Register to Output (Sync) and
- Input to Output(Async). Each path has a start and endpoint
When the clocks are defined, all Register to Register paths are assumed to be
constrained in one clock cycle. A path originates from either an Input port or a
Register clock pin, while an end point is either an Output port or a Register data
pin. All start and end point must be timing constrained.
Calculation of path delays
Calculation of Maximum operating frequency
The maximum running frequency of a digital circuit of single clock domain is calculated based on the
maximum register-to-register delay of each clock domain
The delays in Figure are as follows:
tCQ1: The clock to output delay of the first FF.
tRDQ1: The propagation delay from the first flip-flop output to the input of the second FF.
tCK2: The clock skew which is the timing difference between the arrival of clock edges at the clock inputs of two flip flops
The short-path problem will occur when
tCK2 > tCQ1 + tRDQ1 -tHOLD2
Where tHOLD2 is the hold-time requirement of the sink flip-flop.
The tool lists the paths for each clock domain that are selected by the user. The maximum running frequency of each clock domain is calculated based on the maximum register-to-register delay of each clock domain. It picks the longest register-register path of each clock domain, adds the setup time requirement of the destination register, and considers it as the maximum clock frequency.
The user can apply constraints on the clock frequency. Based on the user's clock period requirement, the tool calculates the maximum allowed register-to-register path delay based on the following equation,
max reg-to-reg path delay = clock period requirement – setup time requirement + clock skew
