#1: When modeling sequential logic, use non-blocking assignments.
#2: When modeling latches, use non-blocking assignments.
#3: When modeling combinational logic with an always block, use blocking assignments.
#4: When modeling both sequential and combinational logic within the same always block, use
non-blocking assignments.
#5: Do not mix blocking and non-blocking assignments in the same always block.
#6: Do not make assignments to the same variable from more than one always block.
#7: Use $strobe to display values that have been assigned using non-blocking assignments.
#8: Do not make assignments using #0 delays.
Following the above guidelines will accurately model synthesizable hardware while eliminating 90-100% of the most common Verilog simulation race conditions.
Reference :: http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
