What is Clock domain crossing ?
When a signal or a set of signals requires (due to functionality, data transfer, control info. transfer etc ) to traverse from one block (working in one clock domain) to another block (working in another clock domain), In such a case, clock domain crossing of signal(s) takes place.
Why 2 blocks may need to work on different clocks ?
There can be different practical reasons for the same like ::1. Inside a chip, Some IP can be custom designed (All Steps in VLSI design flow already done and we have a good working IP) to work on one particular frequency to meet the timing requirements of the IP. But It is quite possible, that the IPs with which this IP is interacting can work fine on either faster or slower clocks. so they will be working at different frequencies. So, clock domain crossing scenerios will arise in such a case.
2. Some IPs are usually bought from other companies and these IPs are also custom designed to work on some particular frequency only.
What problems may arise due to clock domain crossing of signals ?
1. Metastability (Discussed earlier)How to resolve issues arising because of clock domain crossing ?
Using different types of synchronizers at the boundary.
More details to follow ............
