FIFO DESIGN ........

FIFO Design is one of the very tricky & critical design problem ...
First question is ......
Q. Why do we require FIFOs in our design ?
A. Answer to this quest. is whereever we need to transfer multi-bit data from one clock-domain to another,
     that too for mostly asynchronous clock domains i.e. whereever asynchronous clock-domain-crossing is
     involved otherwise there can be issues like data Incoherency or data loss.

     Thus, FIFO is basically used to take-in n-bit data say Data In from some block at say ClockA rate
     and then give-out the n-bit data say Data Out to some other block at Clock B rate as shown below.

     Now What are these FIFO Full and FIFO Empty doing in the figure above ?
     ............................................................
     ..............think ...........think ..................

     As we are writing data in this FIFO at some rate and reading data at some other rate, there is always
     a possibility of FIFO getting totally filled with input data. So, in such a case, there should be some way to
     inform the input Block Not to send any more data. FIFO Full signal is just meant for that purpose.
     Similarly FIFO Empty is there to let the receiving block know that there is no more data to be read now.

     Now, How to generate these FIFO Full and FIFO Empty signals correctly ?
     ## This is the most tricky part of the FIFO design. :)
     ## Try to work out on this .... it will open up many things for you ....

     For those who are crazy to quickly know ............
     Consider the below diagram for understanding FIFOdesign precisely ::