Tuesday, June 8, 2010

Sequential Circuit Design


What is the difference between a Latch and a flip flop?

Latches and Flip-Flops are an important building block in digital circuits
as they provide a way to store state information. Latches and Flip-Flops
are similar in function except with the notable difference that Flip-Flops
take into account the clock. Flip flops are edge sensitive whereas latches
are level sensitive i.e. the output of flip flops can change only on the
occurance of the clock edge whereas the output of the latch can change
anytime during the high or low level of the clock signal depending upon
the sensitivity of the latch.

Write down the VHDL code of following:
(a) D-flip flop
(b) JK flip flop
(a)library ieee ;
use ieee.std_logic_1164.all;
use work.all;
entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff;

architecture behv of dff is
begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then
data_out <= data_in; end if; end process; end behv;

(b)
entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;

-----------------------------------------------

architecture behv of JK_FF is

-- define the useful signals here

signal state: std_logic;
signal input: std_logic_vector(1 downto 0);

begin

-- combine inputs into vector
input <= J & K; p: process(clock, reset) is begin if (reset='1') then state <= '0'; elsif (rising_edge(clock)) then -- compare to the truth table case (input) is when "11" =>
state <= not state; when "10" =>
state <= '1'; when "01" =>
state <= '0'; when others =>
null;
end case;
end if;

end process;

-- concurrent statements
Q <= state; Qbar <= not state; end behv;


What is shift register. Write the VHDL code of Shift register ?

library ieee ;
use ieee.std_logic_1164.all;

entity shift_reg is
port( I: in std_logic;
clock: in std_logic;
shift: in std_logic;
Q: out std_logic
);
end shift_reg;

architecture behv of shift_reg is

-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";

begin

process(I, clock, shift, S)
begin

-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1); end if; end if; end process;

-- concurrent assignment
Q <= S(0); end behv;


Design a counter using VHDL ?

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

----------------------------------------------------

entity counter is

generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;

----------------------------------------------------

architecture behv of counter is

signal Pre_Q: std_logic_vector(n-1 downto 0);

begin

-- behavior describe the counter

process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q; elsif (clock='1' and clock'event) then if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;

-- concurrent assignment statement

Q <= Pre_Q;
end behv;

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