Verilog blocking non-blocking coding guidelines

#1: When modeling sequential logic, use non-blocking assignments.
#2: When modeling latches, use non-blocking assignments.
#3: When modeling combinational logic with an always block, use blocking assignments.
#4: When modeling both sequential and combinational logic within the same always block, use      
       non-blocking assignments.
#5: Do not mix blocking and non-blocking assignments in the same always block.
#6: Do not make assignments to the same variable from more than one always block.
#7: Use $strobe to display values that have been assigned using non-blocking assignments.
#8: Do not make assignments using #0 delays.

Following the above guidelines will accurately model synthesizable hardware while eliminating 90-100% of the most common Verilog simulation race conditions.

Reference :: http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

Clock Domain Crossing

What is Clock domain crossing ?

When a signal or a set of signals requires (due to functionality, data transfer, control info. transfer etc ) to traverse from one block (working in one clock domain) to another block (working in another clock domain), In such a case, clock domain crossing of signal(s) takes place. 

Why 2 blocks may need to work on different clocks ? 

There can be different practical reasons for the same like ::

1. Inside a chip, Some IP can be custom designed (All Steps in VLSI design flow already done and we have a good working IP) to work on one particular frequency to meet the timing requirements of the IP. But It is quite possible, that the IPs with which this IP is interacting can work fine on either faster or slower clocks. so they will be working at different frequencies. So, clock domain crossing scenerios will arise in such  a case.

2. Some IPs are usually bought from other companies and these IPs are also custom designed to work on some particular frequency only.

What problems may arise due to clock domain crossing of signals ?

1. Metastability (Discussed earlier)

How to resolve issues arising because of  clock domain crossing ?

Using different types of synchronizers at the boundary.

More details to follow ............

VERILOG :: Widely used Hardware Description Language - Important Concepts (Initial draft)

1. Each bit in a register can take on one of four values: 0, 1, x, or z. These are the only values a        register can contain.

2.  Is this declaration of registers correct ?
      reg [5:0] x, [5:0] y;
      No !!
      reg [5:0] x, y;
     This is Correct !!

3.  and (a,b,c), (d,e,f);  
     This is also correct instantiation of AND gate !!

4. The primary rule with continuous assignments is that the left-hand side must be a net. The reason for this rule is that registers get values at discrete times, but nets are always driven by a value. Changes to a net may happen asynchronously, any time anything on the right-hand side changes, the left-hand side may change its value

5. Continuous assignments are very similar to port connections between parent and child modules

6. Time can elapse during the execution of a task, according to time and event controls in the task definition

7. Function arguments are also restricted to inputs only. Output and inout arguments are not allowed

System On Chip Architecture

SOC covers many topics

– processor: pipelined, superscalar, VLIW, array, vector
– storage: cache, embedded and external memory
– interconnect: buses, network-on-chip
– impact: time, area, power, reliability, configurability
– customisability: specialized processors, reconfiguration
– productivity/tools: model, explore, re-use, synthesise, verify
– examples: crypto, graphics, media, network, comm, security
– future: autonomous SOC, self-optimising/verifying design

THE NEED OF FORMAL VERIFICATION

In VLSI design flow, the Verification tasks on Chip-RTL and Synthesis on the Chip-RTL
are done Parrallely by different teams. There is a Point in the Design cycle when the RTL gets freezed - which means the Chip-RTL will not be re-synthesized after that.

But the Verification activities are going on as usual which may lead to identification of bugs or connectivity issues between different blocks of the Chip.

Now, these bugs or identified connectivity issues are also to be implemented in RTL-code as well as synthesized RTL (Netlist).

There are tools for doing so. These tools add gates, wires, flip flops etc in the Synthesized Netlist as per the Bug or connectivity issue.

Formal Verification is the Process of Verifying that there is no mismatch between the Synthesized Netlist and Updated/corrected RTL Code and both are equivalent.

As Updated/Corrected RTL is approved by the Design Verification Team , Formal verification is a sure-shot method of verifying that the smae changes are implemented in the Synthesized RTL (Netlist) which is the one to be finally given to Physical Design Team for Final Product/Chip implementation.

Some Limitations of Static Timing Analysis

Practical Approach to Static Timing Analysis

STATIC TIMING ANALYSIS CAN BE PERFORMED AT DIFFERENT STAGES OF THE VLSI DESIGN FLOW AS EXPLAINED BELOW IN THE DIAGRAM -

Interesting Digital design Problems

1.  Design a digital circuit (with minimum logic) to detect the No. of 1's in 8-bit Vector Input signal ?
     Then, try to generalize the circuit for any n-bit input vector ?

2.  Design a digital circuit to detect "1010111100000......................upto 100 bits" (Take Any Pattern)
     with minimum possible logic ?

3.  Design a digital circuit with following specification ::
     
    INPUTS :
    Data_in[7:0]  :           8-bit Data stream coming in continously at clk 10 mhz -
    Master_Key[23:0] :     16-bit key (fixed for the entire operation of the circuit)

    OUTPUTS:
    Data_out[7:0] :         8-bit Data sream coming out continously at clk 10 mhz

   For (First Input Byte at Data_in[7:0])
    { If { Data_in[7:0]  > = Master_Key[23:16] } then
         Data_out[7:0] = Data_in[7:0]  xor  Master_Key[23:16]
      else
         Data_out[7:0] = Data_in[7:0]  xor  Master_key[15:8]
      end }

   For {Second Input Byte at Data_in[7:0]}
     { If { Data_in[7:0]  >= Master_Key[23:16] } then
         temp_var[7:0]  =    Data_in[For first byte]   xor  Master_Key[15:8]
         Data_out[7:0]    =    temp_var1[7:0]  xor  Data_out[For First input byte]
      else
         temp_var[7:0]  =    Data_in[For first byte]   xor  Master_Key[15:8]
         Data_out[7:0]   =  temp_var1[7:0]  xor  Master_key[7:0]
      end }
   
   For {Third Input Byte at Data_in[7:0]}
     { If { Data_in[7:0]  >= Master_Key[23:16] } then
         temp_var[7:0]  =    Data_in[For Second byte]   xor  Master_Key[15:8]
         Data_out[7:0]   =  temp_var[7:0]  xor  Data_out[For second input byte]
      else
         temp_var[7:0]  =    Data_in[For Second byte]   xor  Master_Key[15:8]
         Data_out[7:0] =  temp_var[7:0]  xor  Data_out[For First input byte]
      end }

  // For All Inputs from fourth Byte onwards (fourth Byte included)
   For {Fourth Input Byte Onwards}
    {If { Data_in[7:0]  >= Master_Key[23:16] } then
         temp_var[7:0]  =    Data_in[For Previous Byte]   xor  Master_Key[15:8]
         Data_out[7:0] = temp_var[7:0]  xor  Data_out[For Previous Byte]
      else
        temp_var[7:0]  =    Data_in[For Previous Byte]   xor  Master_Key[15:8]
         Data_out[7:0] =  temp_var[7:0]  xor  Data_out[For Pre-Previous Byte]
      end }

Where, Pre-Previous means " Output byte before the previous output byte"

                 

Static Timing Analysis

Introduction

Static timing analysis is an important step in VLSI design flow for analyzing the performance
of a digital design. Static Timing Analysis is a technique for estimating the delay, maximum
operating frequency of a digital circuit and finding any timing violations in the digital circuit 
without simulation by ensuring that every register to register path in the design does not 
violate the setup and hold time of every flip flop. An accurate and efficient static timing 
analysis has many benefits, such as providing quick and efficient information to enhance the
design performance and easing the design debugging procedure. The basic concepts required
for understanding the complete Static Timing Analysis are discussed first. These concepts are
Set Up and Hold Time Violations, False Paths, Multicycle paths and Clock skew.These concepts
are then used to understand the calculations of path delay, maximum operating frequency and
the requirements for the correct working of the digital circuit.

Set Up and Hold Time Violations

It is a fundamental design principle that timing must satisfy every flip-flop's setup and hold time
requirements, otherwise the flip-flop may go into metastable state ,where the output of flip flop
is unpredicatble. Set up time is the time period for which the data at the data input of the flip 
flop must remain stable before the triggering of the flip-flop by clock edge.

Setup violations occurs when the data path is too slow compared to the clock speed. 

The best way to fix the setup violations is by reducing the delay in the data path

Hold time is the time period for which the data at the data input 

of the flip flop must remain stable after the triggering of the flip-flop by clock edge.

Hold violations occurs when data is too fast when compared to the clock speed.

Hold violations can be fixed by adding more delay to the data path.

False paths

A false path is a path, which exists in the chip but it would never be exercised in the operation of the chip. STA tools can report violations on false paths because there is no knowledge of circuit function. so STA tools needs to be informed about false paths in the circuit so that it should not report any violation. As the STA tool determines delay, it considers only the paths that actually affect the output. If the path is never activated or sensitized, it can't contribute to the delay. Any path that doesn't change or doesn't affect the operation of the circuit should be labeled as false path

Multi-Cycle Paths

A Multi-cycle path in a design is a Register-to-Register path, through some combinational logic where if the source register changes, the path will require N number of clock cycles (where N>1) before the computation is propagated to the destination register



Clock Skew

clock skew is a phenomenon in synchronous circuit in which the clock signal arrives 
at different flip flops at different times. This can be caused by many different things, 
such as wire-interconnect length, clock gating, temperature variations and differences in input 
capacitance on the clock inputs of devices using the clock. The clock skew can be 
positive or negative depending on how the clock-tree is made for the circuit.
clock skew plays an important role in determining the maximum operating frequency of the circuit.

Timing Constraints

Timing constraints are how the designer tells the STA tool about the timing behavior
of the ASIC. The three minimum constraints are defining the clock, input delay, and
output delay. There are four types of timing paths available. They are :

• Input to Register (Sync),
• Register to Register (Sync),
• Register to Output (Sync) and
• Input to Output(Async). Each path has a start and endpoint

When the clocks are defined, all Register to Register paths are assumed to be
constrained in one clock cycle. A path originates from either an Input port or a
Register clock pin, while an end point is either an Output port or a Register data
pin. All start and end point must be timing constrained.


Calculation of path delays






Calculation of Maximum operating frequency

The maximum running frequency of a digital circuit of single clock domain is calculated based on the
maximum register-to-register delay of each clock domain



The delays in Figure are as follows:

1. tCQ1: The clock to output delay of the first FF.
2. tRDQ1: The propagation delay from the first flip-flop output to the input of the second FF.
3. tCK2: The clock skew which is the timing difference between the arrival of clock edges at the clock inputs of two flip flops

The short-path problem will occur when

tCK2 > tCQ1 + tRDQ1 -tHOLD2

Where tHOLD2 is the hold-time requirement of the sink flip-flop.
The tool lists the paths for each clock domain that are selected by the user. The maximum running frequency of each clock domain is calculated based on the maximum register-to-register delay of each clock domain. It picks the longest register-register path of each clock domain, adds the setup time requirement of the destination register, and considers it as the maximum clock frequency.

The user can apply constraints on the clock frequency. Based on the user's clock period requirement, the tool calculates the maximum allowed register-to-register path delay based on the following equation,

max reg-to-reg path delay = clock period requirement – setup time requirement + clock skew

Metastability .......

There are 2 parameters associated with every flip-flop - setup and hold time.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable (in between 0 and 1) : this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. The below diagram explains it better ::

But the question is why does flip-flop goes into metastable state whenever set-up or hold time is violated ?

To answer this, we should understand the internal working of flipflop at the transistor level.

Consider the flip-flop in Figure below. Assume that the clock is low, node A is at 1, and input D changes from 0 to 1. As a result, node A is falling and node B is rising. When the clock rises, it disconnects the input from node A and closes the A B loop. If A and B happen to be around their metastable levels, it would take them a long time to diverge toward legal digital values.In fact, one popular definition says that if the output of a flip-flop changes later than the nominal clock-to-Q propagation delay, then the flip-flop must have been metastable

some solutions to the problem of metastability ::

1. Using faster flipflops decreases the setup and hold times of the flipflop, which in turn

decreases the time window that the flipflop is vulnerable to metastability

2. Using 2 flop/ 3 flop Synchronizers

VHDL: Rules for Variables and Variable Use

Variables are objects used to store intermediate values between sequential VHDL statements.
Variables are allowed only in processes, functions and procedures and are always local to them.
Variables are much like variables in conventional software programming language.
They immediately take on and store the value assigned to them.

Variables are commonly not understood and are therefore not used much.Variables can be
very powerful when used correctly. Here we explain on how to properly use variables. Variables are used to carry combinatorial signals (when used properly, otherwise they can infer sequential logic also) within a process.Variables are updated differently than signals in simulation and synthesis.

In simulation, variables are updated immediately, as soon as an assignment is made.This differs from how signals are updated in simulation. Signals are not updated until all processes that are scheduled to run in the current delta cycle have executed. A variable can be used to carry a combinatorial signal within both a clocked process and a combinatorial process.
This is how synthesis tools treat variables – as intended combinatorial signals but the way coding is done can change the synthesis results. Especially, the order in which signal and variable assignments are made results in the difference.

Figure below shows how to use a variable correctly.  In this case, the variable v maintains its combinatorial intent of a simple two-input and-gate that drives an input to an or-gate for both the a and b registers.

Figure:: Correct Use of Variables

In Figure below, you read from the variable incorrect_v before you assign to it. Thus, incorrect_v uses its previous value, therefore inferring a register because that's the only way to have previous value available inside Sequential process. Had this been a combinatorial process, a latch would have been inferred.

Figure:: Incorrect Use of Variables

Conclusion/Rule for variable usage ::

Always make an assignment to a variable before it is read. Otherwise, variables will infer either latches (in combinatorial processes) or registers (in clocked processes) to maintain their previous value.  The primary intent of a variable is for a combinatorial signal. 

FIFO DESIGN ........

FIFO Design is one of the very tricky & critical design problem ...
First question is ......
Q. Why do we require FIFOs in our design ?
A. Answer to this quest. is whereever we need to transfer multi-bit data from one clock-domain to another,
     that too for mostly asynchronous clock domains i.e. whereever asynchronous clock-domain-crossing is
     involved otherwise there can be issues like data Incoherency or data loss.

     Thus, FIFO is basically used to take-in n-bit data say Data In from some block at say ClockA rate
     and then give-out the n-bit data say Data Out to some other block at Clock B rate as shown below.

     Now What are these FIFO Full and FIFO Empty doing in the figure above ?
     ............................................................
     ..............think ...........think ..................

     As we are writing data in this FIFO at some rate and reading data at some other rate, there is always
     a possibility of FIFO getting totally filled with input data. So, in such a case, there should be some way to
     inform the input Block Not to send any more data. FIFO Full signal is just meant for that purpose.
     Similarly FIFO Empty is there to let the receiving block know that there is no more data to be read now.

     Now, How to generate these FIFO Full and FIFO Empty signals correctly ?
     ## This is the most tricky part of the FIFO design. :)
     ## Try to work out on this .... it will open up many things for you ....

     For those who are crazy to quickly know ............
     Consider the below diagram for understanding FIFOdesign precisely ::

   

   
   

State Machine Design

Lets consider some sample problems which are best solved by State Machine designs...

1. If we have to design a digital logic to detect the sequence "10" in the input bit-stream ...
2. If Master M wants to communicate with Slave S, then Slave S can recognize the
    Master A out of many  masters by detecting some pattern.
    Let that pattern be Hex "F687" ...
3. If we have to detect the Even/odd No. of 1's in the input bit stream ...
4. If we have say, 5-bit input data and we have to detect the event -> " When the Sum
    of the 5-bit input data  is divisible by 5/7/9 etc "
5. State machines can also be used to generate source data at a rate, such that it is stable for at least
    1 complete cycle of the destination clock

There can be many such Problems in Real Chips which are resolved using State Machine design concepts only or In-addition to other concepts ....

Now, The question is .......

How State Machine design is done ?

1. Step 1 is to identify the No. of states that will be required to implement a state machine.
    This will depend on the kind of state machine you are going to build. For e.g. for
    detecting a sequence of  bits like "10" in the input bit-stream,
    How many states you will require ........?
    ....................................
    ..................................
    Think about it  ...........
     ..................................
     Think, if you can implement with lesser No. of states
     ...................................
     ..................................
2.  Now start from first state. This be the state when system starts after reset.
     Let first state name be = initial
     Conside both 1 and 0 inputs at this state and decide what should happen
     on receiving both the inputs respectively.
     In General, If we are moving closer to fully detect the pattern (means if we have 
     partially detected some part [few bit(s))of the full pattern] then we have to 
     move to the next state, otherwise we have to either stay at the same stay or we 
     have to move back to one state up OR 2 states up OR 3 states up depending on 
     the complete  pattern to be detected. 
    Few examples and some practice will clear this concept concisely.

     Another important aspect of the state machine design is whether we want the 
     output (to indicate PATTERN DETECTED ) to be High during transition b/w
     particular states or just For a particular State.
     This leads us to 2 types of state machines - Mealy OR Moore respectively.
      .........................
      Can you try to find which type of state machine will have more states ?
      ...........................
      ...........................
     
       For the pattern "10" detection, Below is our first state machine :

      Similarly, You can try creating Both Mealy and Moore machines for the examples
      given at the beginning of this topic.
      ## Remember Practice makes the man perfect

       Lets have some more discussion on these two types of state machines ::

       Mealy Machine ::

       - In a Mealy machine, the outputs are a function of the present state and the
          value of the inputs as shown in figure above.
ƒ       - Accordingly, the outputs may change  asynchronously in response to any
         change in the inputs .
          Why Asynchronously ? Think ...........
          Can you think of the kind of the Circuit the mealy machine will have ?
           .....................................

        Moore Machine ::

        - In a Moore machine the outputs depend only on the present state as shown in
           figure below.
        - More states than mealy but output is Synchronous with state

Quests to think about ........

          1. How can we map the states with the actual digital logic design elements ?
          2. Does more states means more logic is reqd. ?

VHDL Miscellaneous Questions

Describe the Skeleton of a Basic VHDL Program ?

The VHDL program contains Entity, Architecture , Configuration
and library.

The declaration part is optional and can include internal signal declarations or constant
declarations
There are many possibilities for concurrent_stmts, which we will cover soon
Other design units (beyond entity and architecture) include
• Package declaration & body
A package is a collection of commonly used items, such as data types, subprograms
and components
• Configuration
An entity declaration can be associated with multiple architecture bodies
A configuration enables one of them to be instantiated during synthesis
A VHDL library is a place to store design units
The default library is ’work


What are VHDL Objects ?

An object is a named element that holds a value of specific data type.
There are four kinds of objects :-

• Signal
• Variable
• Constant
• File (cannot be synthesized)

What are the various liabraries used in VHDL Programming ?

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee.std_logic_signed.all;

Use ieee.std_logic_unsigned.all;

What ar the Various data types used in VHDL ?

bit values: '0', '1'

boolean values: TRUE, FALSE

integer values: -(231) to +(231 - 1)

Std_logic values: 'U','X','1','0','Z','W','H','L','-'

'U' = uninitialized

'X' = unknown

'W' = weak 'X‘

'Z' = floating

'H'/'L' = weak '1'/'0‘

'-' = don't care

Std_logic_vector (n downto 0);

Std_logic_vector (0 upto n);

What do you mean by RTL ?

RTL consists of a language which describes behavior in -

1.asynchronous and synchronous state machines

2.data paths

3.operators (+,*,<,>,...)

4.registers

Explain Architecture declaration region ?

The architecture declaration part must be defined before first begin
and can consist of, for example:

1.types

2.subprograms

3.components

4.signal declarations

Few Other Basic Concepts of VHDL :-

1. We can use the same signal names, the formals: Sum , X , Y , and Cout, in the architecture as we use in the entity
2. An architecture can refer to other entity-architecture pairs (i.e., we can nest black boxes)
3. Input port can only be read inside architecture

4. Functions and procedures are important parts of the language in order to handle complexity
5. Inout is used for Component read or write to the signal (bidirectional signals)
6. Output port can only be written inside architecture

7. Multiple signal assignment statements are executed concurrently in simulated time

Sequential Circuit Design

What is the difference between a Latch and a flip flop?

Latches and Flip-Flops are an important building block in digital circuits
as they provide a way to store state information. Latches and Flip-Flops
are similar in function except with the notable difference that Flip-Flops
take into account the clock. Flip flops are edge sensitive whereas latches
are level sensitive i.e. the output of flip flops can change only on the
occurance of the clock edge whereas the output of the latch can change
anytime during the high or low level of the clock signal depending upon
the sensitivity of the latch.

Write down the VHDL code of following:
(a) D-flip flop
(b) JK flip flop(a)library ieee ;
use ieee.std_logic_1164.all;
use work.all;
entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff;

architecture behv of dff is
begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then
data_out <= data_in; end if; end process; end behv;
(b) entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;

-----------------------------------------------

architecture behv of JK_FF is

-- define the useful signals here

signal state: std_logic;
signal input: std_logic_vector(1 downto 0);

begin

-- combine inputs into vector
input <= J & K; p: process(clock, reset) is begin if (reset='1') then state <= '0'; elsif (rising_edge(clock)) then -- compare to the truth table case (input) is when "11" =>
state <= not state; when "10" =>
state <= '1'; when "01" =>
state <= '0'; when others =>
null;
end case;
end if;

end process;

-- concurrent statements
Q <= state; Qbar <= not state; end behv;

What is shift register. Write the VHDL code of Shift register ?

library ieee ;
use ieee.std_logic_1164.all;

entity shift_reg is
port( I: in std_logic;
clock: in std_logic;
shift: in std_logic;
Q: out std_logic
);
end shift_reg;
architecture behv of shift_reg is

-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";

begin

process(I, clock, shift, S)
begin

-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1); end if; end if; end process;
-- concurrent assignment
Q <= S(0); end behv;

Design a counter using VHDL ?
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

----------------------------------------------------

entity counter is

generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;

----------------------------------------------------

architecture behv of counter is

signal Pre_Q: std_logic_vector(n-1 downto 0);

begin

-- behavior describe the counter

process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q; elsif (clock='1' and clock'event) then if count = '1' then

Pre_Q <= Pre_Q + 1;

end if;

end if;

end process;

-- concurrent assignment statement

Q <= Pre_Q;

end behv;

Combinational Circuit design

What is the difference between encoder and multiplexer? Write VHDL code for both ?


An encoder is a device used to change a signal (such as a bitstream)
or data into a code.Encoders work in exactly the opposite way as decoders,
taking 2^N inputs, and having N outputs. When a bit comes in on an input
wire, the encoder outputs the physical address of that wire.

A multiplexer combines multiple inputs into one output.
It selects the input, depending on the inputs at
select lines and sends the selected input to the output.
e.g. 4:1 , 2:1 multiplexor.

--------Multiplexer ----------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;

architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
begin

-- use case statement
case S is
when "00" => O <= I0; when "01" => O <= I1; when "10" => O <= I2; when "11" => O <= I3; when others => O <= "ZZZ"; end case; end process; end behv1; architecture behv2 of Mux is begin O <= I0 when S="00" else I1 when S="01" else I2 when S="10" else I3 when S="11" else "ZZZ"; end behv2;


What is the difference between decoder and demultiplexer ? Write VHDL code for both ?

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;

architecture behv of DECODER is
begin

-- process statement

process (I)
begin

-- use case statement

case I is
when "00" => O <= "0001"; when "01" => O <= "0010"; when "10" => O <= "0100"; when "11" => O <= "1000"; when others => O <= "XXXX"; end case;

end process;

end behv;

architecture when_else of DECODER is begin

-- use when..else statement O <= "0001" when I = "00" else "0010" when I = "01" else "0100" when I = "10" else "1000" when I = "11" else "XXXX"; end when_else;

VHDL Interview Questions 1

What do you mean by HDLs ?

Hardware description language or HDL is any language from a class of
computer languages and/or programming languages for formal description of
electronic circuits, and more specifically, digital logic. It can describe the
circuit's operation, its design and organization, and tests to verify its operation
by means of simulation. HDLs are standard text-based expressions of the spatial
and temporal structure and behaviour of electronic systems. Like concurrent
programming languages, HDL syntax and semantics includes explicit notations for
expressing concurrency. However, in contrast to most software programming
languages,HDLs also include an explicit notion of time, which is a primary attribute
of hardware Languages whose only characteristic is to express circuit connectivity
between a hierarchy of blocks are properly classified as netlist languages used on
electric computer-aided design .VHDL and VERILOG are the two most widely
used Hardware description languages .

What is VLSI Design ?
VLSI Design stands for Very Large scale Integrated circuit design.
Very-large-scale integration (VLSI) is the process of creating integrated circuits
by combining thousands of transistor-based circuits into a single chip
VLSI which involves the packing of more and more logic devices into smaller
and smaller areas.

What is VHDL ? What are capabilities of VHDL ?
VHDL is a programming language, much like C++, it has its own syntax and
semantics. The big difference from traditional programing languages is that
instead of describing instructions which a processor will execute, it describes
how circuits should be organized.VHDL is basically a programming language
used to model digital Systems. As it is emulating real hardware it is inherently
parallel and also treats timing as important. This language is a commonly used
in the design of field-programmable gate arrays(FPGA)and application specific
integrated circuits(ASIC). VHDL stands for Very High Speed Integrated Circuit
Hardware Description language.VHDL is composed of language building blocks
that consist of more than 75 reserved words and about 200 descriptive
words or word combinations.

What can be the various uses of VHDL ?

The VHDL language can be used for several goals like -

i) To synthesize digital circuits

ii) To verify and validate digital designs

iii) To generate test vectors to test circuits

iv) To simulate circuits

What are the Various levels of abstractions in VLSI design?
Abstraction is defined as the hiding of information that is too detailed.
It is therefore necessary to diffrentiate between essential and
non-essential information. Information that is not important for the
current view of the problem will be left out from the description
The Various levels of abstraction in VLSI design are :-
1. Behaviour level
2. RTL (Register Transfer level)
3. Logic level
4. Layout (Transistor level)

In the behaviour level, complete systems can be modelled. Bus
systems or complex algorithms are described without considering
synthesizability. The stimuli for simulation of RTL models are described
in the behaviour level, for example. Stimuli are signal values of the
input ports of the model and are described in the testbench,
sometimes called validation bench.

The designer has to take great care to find a consistent set of input
stimuli that do not contradict the specification. The responses of the
model have to be compared with the expected values which, in the
simplest case, can be done with the help of a waveform diagram that
shows the simulated signal values.

On the RT level, the system is described in terms of registers and logic
that calculates the next value of the storage elements. It is possible to
split the code into two blocks (cf. process statement) that contain
either purely combinational logic or registers. The registers are connected
to the clock signal and provide for synchronous behaviour. In practice,
the strict separation of Flip Flops from combinational logic is often
annulated and clocked processes describe the registers and the
corresponding update functions.

The gate netlist is generated from the RT description with the help of a
synthesis tool. For this task, a cell library for the target technology which
holds the information about all available gates and their parameters
(fan-in, fan-out, delay) is needed.

Based upon this gate netlist the circuit layout is generated. The resulting
wire lengths can be converted into propagation delays which can be fed
back into the gate level model (back annotation). This allows for thorough
timing simulations without the need for additional simulator software.

What is Synthesis?

Synthesis represents the transformation of an abstract description into a
more detailed descrition. In general, the term "synthesis" is used for the
automated transformation of RT level descriptions into gate level representations.
This transformation is mainly influenced by the set of basic cells that is available
in the target technology. While simple operations like comparisons and either/or
decisions are easily mapped to boolean functions, more complex constructs like
mathematical operators are mapped to a tool specific macro cell library first.
This means that a number of adder, multiplier, etc. architectures are known
to the synthesis tool and these designs are treated as if they were designed
by the user.

What is the difference between Entity and Architecture ?
Entity
The interface between a module and its environment is described within
the entity declaration which is initiated by the keyword ' entity '. It is
followed by a user-defined descriptive name. The interface description
is placed between the keyword ' is ' and the termination of the entity
statement which consists of the keyword ' end ' and the name of the entity.
The input, output and bi-directional ports are defined in the entity.
In the new VHDL'93 standard the keyword ' entity ' may be repeated after
the keyword ' end ' for consistency reasons.

Architecture
The architecture contains the implementation for an entity which may be
either a behavioural description (behavioural level or, if synthesizable,
RT level) or a structural netlist or a mixture of those alternatives..

An architecture is strictly linked to a certain entity. An entity, however,
may have several architectures underneath, e.g. different
implementations of the same algorithm or different abstraction levels.
Architectures of the same entity have to be named differently in order
to be distinguishable. The name is placed after the keyword ' architecture '
which initiates an architecture statement. 'RTL' was chosen in this case.

It is followed by the keyword ' of ' and the name of entity that is used as
interface ('HALFADDER'). The architecture header is terminated by the
keyword ' is ', like in entity statements. In this case, however, the keyword
' begin ' must be placed somewhere before the statement is terminated.
This is done the same way as in entity statements: The keyword ' end ',
followed by the architecture name. Once again, the keyword ' architecture '
may be repeated after the keyword ' end ' in VHDL'93.

Explain Various types of Modelling styles ?
The Various modelling styles are :-
Structural, behavioural, dataflow and mixed style.

Structural Description Method: It expresses the design as an
arrangement of interconnected components. It is basically the
representation of the schematic in VHDL Language form.

Behavioral Description Method: describes the functional behavior of a
hardware design in terms of circuits and signal responses to various stimuli.

A Behavioral Description uses a small number of processes where each process
performs a number of sequential signal assignments to multiple signals.

The hardware behavior is described algorithmically and this modelling style
is the most frequently used and the best way to model any algorithm.

The advantage of models at this level is that models for simulation can be
built quickly.

Data-Flow Description Method: is similar to a register-transfer language

This method describes the function of a design by defining the flow of
information from one input or register to another register or output.

Data-Flow Description uses a large number of concurrent signal assignment
statements. A concurrent statement executes asynchronously with respect
to other concurrent statements.

The concurrent statements used in data flow description include:-

- block statement (used to group one or more concurrent statements)

- concurrent procedure call- concurrent assertion statement
- concurrent signal assignment statement

Explain various types of delays in VHDL ?
The Various types of delays in VHDL are :-

1. Delta delay - In VHDL simulations, all signal assignments occur with some
infinitesimal delay, known as delta delay. VHDL uses the concept of delta
delay to keep track of processes that should occur at a given time step,
but are actually evaluated in different machine cycles .A delta delay is a
unit of time as far as the simulator hardware is concerned, but in the
simulation itself time has no advance. Technically, delta delay is of no
measurable unit, but from a hardware design perspective one should think
of delta delay as being the smallest time unit one could measure, such as
a femtosecond(fs).

2. Inertial delay - The inertial delay causes the pulses less than specified delay
to get suppressed & will not propogate these pulses to change the output.
The inertial delay model is specified by adding an after clause to the
signal assignment statement. Inertial delay is basically a default delay,
i.e it's a component delay.

3. Transport delay - Tranport delay adds the propogation delay to the signal.
The transport delay model just delays the change in the
output by the time specified in the after clause.
Transport delay basically represents a wire delay.
e.g. q <=transport a nor b after 1ns ;

What are Generics ?
Generics are a way to provide static information to the VHDL program.
Immediately after writing entity name, we will mention the generics,
this generics will provide the data for entire program.
Generics basically allow a design entity to be described so that,for each use
of that component,its structure and behavior can be changed by
generic values.In general they are used to construct parameterized
hardware components.Generics can be of any type.but mostly we will give the timing details there.

E.g. :- generic ( width : integer := 7 );

Generic is a great asset when you use your design at many places with
slight change in the register sizes,input sizes etc. But if the design is very
unique then,you need not have generic parameters. Also, Generic's are
synthesizable.

What is the difference between STD_LOGIC and BIT types?

BIT has 2 values: '0' and '1'.

STD_LOGIC is defined in the library std_logic_1164.This is a nine valued logic system.
It has 9 values: 'U', 'X', '0', '1', 'Z', 'W', 'L' ,'H' and '-'.
The meaning of each of these characters are:
U = uninitialized
X = unknown - a multisource line is driven '0' and '1' simultaneously (*)
0 = logic 0
1 = logic 1
Z = high impedance (tri state)
W = weak unknown
L = weak "0"
H = weak "1"
- = dont care

Type std_logic is unresolved type because of 'U','Z' etc. It is illegal to
have a multi-source signal in VHDL. So use 'bit' logic only when the signals
in the design doesn't have multi sources. If you are unsure about this then
declare the signals as std_logic or std_logic_vector,because then you will
be able to get errors in the compilation stage itself. But many of the operators
such as shift operators cannot be used on 'std_logic_vector' type.So you may
need to convert them to bit_vector before using shift operations.
One example is given below:

example of how to shift a std_logic signal : right shifting logically by 2 bits.
Here, count is std_logic_vector.
output <= To_StdLogicVector(to_bitvector(count) srl 2); to_bitvector converts Std_Logic_Vector to bit_vector. To_StdLogicVector converts bit_vector to Std_Logic_Vec

What is the difference between Concurrent & Sequential Statements ?

Concurrent statements define interconnected processes and blocks that
together describe a design’s overall behavior or structure. They can be grouped
using block statement. Groups of blocks can also be partitioned into other blocks.
At the same level, a VHDL component can be connected to define signals within the blocks
It is a reference to an entity
A process can be a single signal assignment statement or a series of sequential statements (SS)
Within a process, procedures and functions can partition the sequential statements

Discuss process and wait statements? Can they be used simultaneously
in the program ?
-- INCOMPLETE ANSWER
The Various features of the process statement are :-

• It contains sequentially executed statements
• It can exist within an architecture only
• Several processes run concurrently
• Execution is controlled either via
• sensitivity list (contains trigger signals), or
• wait-statements
• The process label is optional

Because the statements within an architecture operate concurrently, therefore another
VHDL construct is necessary to achieve sequential behaviour. A process, as a whole, is
treated concurrently like any other statement in an architecture and contains statements
that are executed one after another like in conventional programming languages. In fact
it is possible to use the process statement as the only concurrent VHDL statement.
The execution of a process is triggered by events. Either the possible event sources are
listed in the sensitivity list or explicit wait statements are used to control the flow of execution.

These two options are mutually exclussive, i.e. no wait statements are allowed in a process
with sensitivity list. While the sensitivity list is usually ignored by synthesis tools, a VHDL
simulator will invoke the process code whenever the value of at least one of the listed signals
changes. Consequently, all signals that are read in a purely combinational process, i.e. that
influence the behaviour, have to be mentioned in the sensitivity list if the simulation is to
produce the same results as the synthesized hardware. Of course the same is true for
clocked processes, yet new register values are to be calculated with every active clock edge,
only. Therefore the sensitivity list contains the clock signal and asynchronous control signals
(e.g. reset).

A process statement starts with an optional label and a ':' symbol, followed by the ' process '
keyword. The sensitivity list is also optional and is enclosed in a '(' ')' pair. Similar to the
architecture statement, a declarative part exists between the header code and the keyword
' begin '. The sequential statements are enclosed between ' begin ' and ' end process '.
The keyword ' process ' has to be repeated! If a label was chosen for the process, it has to
be repeated in the end statement, as well.


What is the difference between Signal and the Variable ?
Signals are interpreted as wires or wires with memory (i.e., FFs, latches etc.)

Signal are declared as :-
signal signal_name, signal_name, ... : data_type

Signal assignment :-
signal_name <= projected_waveform;

The Concept of variables is found in traditional programming languages, in
which a name represents a symbolic memory location where a value can be
stored and modified. There is NO direct mapping between a variable and a
hardware component. Variables can be declared and used only inside a process.

Variable declaration:
variable variable_name, ... : data_type

Variable assignment:
variable_name := value_expression;
Variables contains no timing information (immediate assignment) i.e. no
waveform is possible for variables.
Both signals and variables can be assigned initial values.
Although useful in simulations, synthesis canNOT deal with them

What are VHDL Subtypes ?
VHDL subtypes are used to constrain defined types. Constraints take the
form of range constraints or index constraints. However, a subtype may
include the entire range of the base type. Assignments made to objects
that are out of the subtype range generate an error at run time. The syntax
and an example of a subtype declaration is shown below :-

SUBTYPE First_ten IS INTEGER RANGE 0 to 9;

Explain Resolution Function ?
A resolution function defines how values from multiple sources, multiple drivers,
are resolved into a single value. The signals in VHDL can have multiple drivers.
The value of the signal is a function of all the drivers of that signal. The
following figure shows an example of a bus signal which is driven by four
independent signals. The value bus is computed by a bus resolution
function (brf in this example).

A resolution function must be a pure function that has a single input
parameter of class constant that is a one dimensional unconstrained
array of the type of the resolved signal.

The drivers are labeled s1,s2,s3, and s4. The value of the signal dbus is
computed by a bus resolution function (brf in our example). Bus resolution
functions are user-defined and are evaluated when one of the drivers of the
signal receives a new value (event). The 'resolved' value is then generated
by the bus resolution function

Write short notes on Case statements ?
All branches are equal in priority when using a CASE statement.
Therefore it is obvious that there must not be any overlaps
among cases or choices and all possible values of the CASE EXPRESSION
must be covered. For covering all remaining, i.e. not yet covered,
cases, the keyword ' others ' may be used.

The type of the EXPRESSION in the head of the CASE statement
has to match the type of the query values. Single values of EXPRESSION
can be grouped together with the '|' symbol, if the consecutive action
is the same. Value ranges allow to cover even more choice options
with relatively simple VHDL code.

case EXPRESSION is
when VALUE_1 =>
-- sequential statements
when VALUE_2 | VALUE_3 =>
-- sequential statements
when VALUE_4 to VALUE_N =>
-- sequential statements
when others =>
-- sequential statements
end case ;

Write short note on Loop statement and Next statement ?
Three kinds of iteration statements.

[ label: ] loop
sequence-of-statements -- use exit statement to get out
end loop [ label ] ;

[ label: ] for variable in range loop
sequence-of-statements
end loop [ label ] ;

[ label: ] while condition loop
sequence-of-statements
end loop [ label ] ;

loop
input_something;
exit when end_file;
end loop;

for I in 1 to 10 loop
AA(I) := 0;
end loop;

while not end_file loop
input_something;
end loop;


all kinds of the loops may contain the 'next' and 'exit' statements.

-----------------------------------------------------------------------
A statement that may be used in a loop to cause the next iteration.

[ label: ] next [ label2 ] [ when condition ] ;

next;
next outer_loop;
next when A>B;
next this_loop when C=D or done; -- done is a Boolean variable









Discuss the Difference between array and records types ?

ARRAYS :-VHDL composite types consists of arrays and records. Each object of
this data type can hold more than one value. Arrays consist of many
similar elements of any data type, including arrays. The array is declared
in a TYPE statement. There are numerous items in an array declaration.
The first item is the name of the array. Second, the range of the array is
declared. The keywords TO and DOWNTO designate ascending or descending
indices, respectively, within the specified range. The third item in the array
declaration is the specification of the data type in each element of the array.

E.g :- TYPE data_bus IS ARRAY (0 to 31) OF BIT ;
TYPE reg_type IS ARRAY (15 downto 0) of BIT ;

RECORDS :-

The second VHDL composite type is the record. Records are used to group
elements of different types into a single VHDL object. An object of type record may
contain elements of different types. Again, a record element may be of any data
type, including another record. A TYPE declaration is used to define a record.
Note that the types of a record's elements must be defined before the record
is defined. Also notice that there is no semi-colon after the word RECORD. The
RECORD and END RECORD keywords bracket the field names. After the RECORD
keyword, the record's field names are assigned and their data types are specified.

E.g :- TYPE Switch_info IS
Record
status : binary ;
Idnumber : integer ;
END Record;

switch.status = ON;
switch.IDnumber = 30;


In the above example, a record type, switch_info, is declared. This example makes
use of the binary enumerated type declared previously. Note that values are
assigned to record elements by use of the field name.