Interesting Digital design Problems

1.  Design a digital circuit (with minimum logic) to detect the No. of 1's in 8-bit Vector Input signal ?
     Then, try to generalize the circuit for any n-bit input vector ?

2.  Design a digital circuit to detect "1010111100000......................upto 100 bits" (Take Any Pattern)
     with minimum possible logic ?

3.  Design a digital circuit with following specification ::
     
    INPUTS :
    Data_in[7:0]  :           8-bit Data stream coming in continously at clk 10 mhz -
    Master_Key[23:0] :     16-bit key (fixed for the entire operation of the circuit)

    OUTPUTS:
    Data_out[7:0] :         8-bit Data sream coming out continously at clk 10 mhz

   For (First Input Byte at Data_in[7:0])
    { If { Data_in[7:0]  > = Master_Key[23:16] } then
         Data_out[7:0] = Data_in[7:0]  xor  Master_Key[23:16]
      else
         Data_out[7:0] = Data_in[7:0]  xor  Master_key[15:8]
      end }

   For {Second Input Byte at Data_in[7:0]}
     { If { Data_in[7:0]  >= Master_Key[23:16] } then
         temp_var[7:0]  =    Data_in[For first byte]   xor  Master_Key[15:8]
         Data_out[7:0]    =    temp_var1[7:0]  xor  Data_out[For First input byte]
      else
         temp_var[7:0]  =    Data_in[For first byte]   xor  Master_Key[15:8]
         Data_out[7:0]   =  temp_var1[7:0]  xor  Master_key[7:0]
      end }
   
   For {Third Input Byte at Data_in[7:0]}
     { If { Data_in[7:0]  >= Master_Key[23:16] } then
         temp_var[7:0]  =    Data_in[For Second byte]   xor  Master_Key[15:8]
         Data_out[7:0]   =  temp_var[7:0]  xor  Data_out[For second input byte]
      else
         temp_var[7:0]  =    Data_in[For Second byte]   xor  Master_Key[15:8]
         Data_out[7:0] =  temp_var[7:0]  xor  Data_out[For First input byte]
      end }

  // For All Inputs from fourth Byte onwards (fourth Byte included)
   For {Fourth Input Byte Onwards}
    {If { Data_in[7:0]  >= Master_Key[23:16] } then
         temp_var[7:0]  =    Data_in[For Previous Byte]   xor  Master_Key[15:8]
         Data_out[7:0] = temp_var[7:0]  xor  Data_out[For Previous Byte]
      else
        temp_var[7:0]  =    Data_in[For Previous Byte]   xor  Master_Key[15:8]
         Data_out[7:0] =  temp_var[7:0]  xor  Data_out[For Pre-Previous Byte]
      end }

Where, Pre-Previous means " Output byte before the previous output byte"