VLSI Frontend basics

Q1. What are the Various Tools used in Frontend design ?
A1.  1. Synopsys Design Compiler - For Synthesis {which means converting RTL code (VHDL/Verilog - which represents the digital design) into Gate level netlist (more closer representation of real hardware)}
       2. Atrenta's SpyGlass - For Coding violations , Connectivity issues like Multiple drivers at a port ,Port-width Mismatch, unconnected ports etc
       3. Mentor's 0in-CDC - For Clock Domain crossing violations
       4. Primetime - For Static timing Analysis
       will add more to the list ..............




Q2. VLSI Design flow overview Block diagram ?
A2.